Method of forming a capacitor and method of manufacturing a semiconductor device using the same

ABSTRACT

A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.

PRIORITY STATEMENT

This application claims priority under 35 USC §119 to Korean PatentApplication No. 10-2011-0035878 filed on Apr. 18, 2011 in the KoreanIntellectual Property Office (KIPO), the contents of which are hereinincorporated by reference in their entirety.

BACKGROUND

1. Field

The inventive concept relates to a method of fabricating a capacitor andto a method of manufacturing a semiconductor device including acapacitor.

2. Description of the Related Art

As semiconductor devices become more highly integrated, the footprint ofcapacitors of the devices becomes smaller and yet the capacitors stillmust provide a high capacitance. One way in which a capacitor having asmall footprint can nonetheless provide a high capacity is for thecapacitor to have a high aspect ratio (a high ratio of height to width).In this respect, a capacitor having sides that are vertical(perpendicular) with respect to a substrate, on which the capacitor isformed, is desirable because the height of a capacitor is maximal whenthe sides of the capacitor are vertical.

Typically, a capacitor of a semiconductor device is fabricated byforming a mold layer of an oxide on a substrate, forming an opening inthe mold layer, and then forming a storage electrode along the sides ofthe opening. However, the process used to at least initially form theopening in the mold layer often leaves the opening without verticalsides. In particular, the higher the aspect ratio of the opening, themore difficult it is to form vertical sidewalls that define the sides ofthe opening.

SUMMARY

According to an aspect of the inventive concept, there is provided amethod of manufacturing a capacitor in which a mold layer, comprisingsilicon but excluding oxides of silicon, is form on a substrate, anopening is formed through the mold layer, a barrier layer is formedalong the sides of the opening, a lower electrode is formed in theopening including over the barrier layer, the mold layer and the barrierlayer are then removed, and a dielectric layer and an upper electrodeare sequentially formed on the lower electrode.

According to another aspect of the inventive concept, there is provideda method of manufacturing a capacitor in which a mold layer comprisingdoped or undoped polysilicon is formed on an upper surface of asubstrate, the mold layer is etched to form an opening through the moldlayer, a barrier layer is formed along the sides of the opening, a lowerelectrode is formed in the opening including over the barrier layer, themold layer and the barrier layer are subsequently removed, and adielectric layer and an upper electrode are sequentially formed on thelower electrode.

According to another aspect of the inventive concept, there is provideda method of manufacturing a capacitor in which a transistor is formed atan upper portion of a substrate, an insulating interlayer is formed onthe substrate over the transistor, a contact plug is formed through theinsulating interlayer, at least one mold layer comprising silicon butexcluding oxides of silicon is formed on the insulating interlayer andthe contact plug, an opening is formed through the at least one moldlayer such that the opening exposes top surfaces of the contact plug andthe insulating interlayer, a barrier layer is formed along the sides ofthe opening, a lower electrode is formed in the opening including overthe exposed top surfaces of the contact plug and the insulatinginterlayer, and the barrier layer, then the mold layer and the barrierlayer are removed, and a dielectric layer and an upper electrode aresequentially formed on the lower electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concept will be more clearly understood from the followingdetailed description of the preferred embodiments thereof taken inconjunction with the accompanying drawings.

FIGS. 1 to 7 are cross-sectional views illustrating one embodiment of amethod of forming a capacitor in accordance with the inventive concept;

FIGS. 8 to 13 are cross-sectional views illustrating another embodimentof a method of forming a capacitor in accordance with the inventiveconcept;

FIGS. 14 to 19 are cross-sectional views illustrating yet anotherembodiment of a method of forming a capacitor in accordance with theinventive concept; and

FIGS. 20 to 24 are cross-sectional views illustrating a method ofmanufacturing a semiconductor device in accordance with the inventiveconcept.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments and examples of embodiments of the inventive conceptwill be described more fully hereinafter with reference to theaccompanying drawings. In the drawings, the sizes and relative sizes andshapes of elements, layers and regions, such as implanted regions, shownin section may be exaggerated for clarity. In particular, thecross-sectional illustrations of the semiconductor devices andintermediate structures fabricated during the course of theirmanufacture are schematic. Also, like numerals are used to designatelike elements throughout the drawings.

It will also be understood that when an element or layer is referred toas being “on” another element or layer, it can be directly on the otherelement or layer or intervening elements or layers may be present. Incontrast, when an element or layer is referred to as being “directly on”or in contact with another element or layer, there are no interveningelements or layers present.

Furthermore, spatially relative terms, such as “upper,” and “lower” areused to describe an element's and/or feature's relationship to anotherelement(s) and/or feature(s) as illustrated in the figures. Thus, thespatially relative terms may apply to orientations in use which differfrom the orientation depicted in the figures. Obviously, though, allsuch spatially relative terms refer to the orientation shown in thedrawings for ease of description and are not necessarily limiting asembodiments according to the inventive concept can assume orientationsdifferent than those illustrated in the drawings when in use.

Other terminology used herein for the purpose of describing particularexamples or embodiments of the inventive concept is to be taken incontext. For example, the terms “comprises” or “comprising” when used inthis specification specifies the presence of stated features orprocesses but does not preclude the presence or additional features orprocesses.

A first embodiment of a method of forming a capacitor in accordance withthe inventive concept will now be described with respect to FIGS. 1 and7.

Referring first to FIG. 1, an insulating interlayer 110 is formed on asubstrate 100.

The substrate 100 is a semiconductor substrate. For example, thesubstrate 100 may be a silicon (Si) substrate, a germanium (Ge)substrate, a silicon-germanium (Si—Ge) substrate, a silicon-on-insulator(SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc. Thesubstrate 100 may also be of material doped with n-type or p-typeimpurities.

The insulating interlayer 110 may be formed of an oxide such as siliconoxide. For example, the insulating interlayer 110 may be formed of atleast one of boro-phosphor silicate glass (BPSG), undoped silicate glass(USG), and spin on glass (SOG). Accordingly, the insulating interlayer110 may be formed by a chemical vapor deposition (CVD) process or aphysical vapor deposition (PVD) process.

Additionally, a plug 120 is formed through the insulating interlayer110. For example, the insulating interlayer 110 is etched to form a hole(not shown) exposing a top surface of the substrate 100, and aconductive layer is formed on the substrate 100 and the insulatinginterlayer 110 to such a thickness as to fill the hole. In this respect,the conductive layer may be formed of doped polysilicon or a metal by aCVD process, a PVD process, an atomic layer deposition (ALD) process orthe like. Then the conductive layer may be planarized by a chemicalmechanical polishing (CMP) process and/or an etch-back process until theupper surface of the insulating interlayer 110 is exposed and the plug120 is left filling the hole.

Referring to FIG. 2, an etch stop layer 130 and a mold layer 140 aresequentially formed on the insulating interlayer 110 and the plug 120.

The etch stop layer 130 may be formed of silicon nitride by a CVDprocess, a PVD process, an ALD process, or the like.

The mold layer 140 is formed of a silicon non-oxide material, e.g.,amorphous silicon, amorphous silicon doped with impurities, polysilicon,or polysilicon doped with impurities. Thus, the mold layer 140 may beformed by a CVD process, a PVD process, or the like. The impurities thatmay be employed include carbon (C), boron (B), phosphorous (P), nitrogen(N), aluminum (Al), titanium (Ti), oxygen (O), and arsenic (As). In anexample of this embodiment, the mold layer 140 has a thickness equal toor more than 1 μm.

Referring to FIG. 3, parts of the mold layer 140 and the etch stop layer130 are removed to form an opening 145 exposing a top surface of theplug 120. At this time, part of the top surface of the insulatinginterlayer 110 may be exposed by the opening 145.

Specifically, a portion of the mold layer 140 may be dry etched to formthe opening 145, using a photoresist pattern (not illustrated) as anetching mask, until the etch stop layer 130 is exposed. As examples ofsuch a dry etching process, the mold layer 140 is etched by an etchinggas comprising hydrogen fluoride (HF), hydrogen bromide (HBr),tetrafluoromethane (CF₄), hexafluoroethane (C₂F₆), trifluoromethane(CHF₃), difluoromethane (CH₂F₂), methyl bromide (CH₃Br),chlorotrifluoromethane (CClF₃), trifluorobromomethane (CBrF₃), carbontetrachloride (CCl₄), sulfur hexafluorid (SF₆), chlorine (Cl₂), ornitrogen trifluorude (NF₃). Alternatively, the mold layer 140 may be wetetched, to form the opening 145, by a solution of hydrogen fluoride(HF), ammonium hydroxide (NH₄OH), potassium hydroxide (KOH), or sodiumhydroxide (NaOH), for example, or a buffered oxide etch (BOE) solution.

The etch stop layer 130 is provided as a means to terminate this part ofthe etching process for forming the opening 145. However, the exposedportion of the etch stop layer may be removed to complete the opening145. To this end, the etch stop layer 130 may be etched by an etchinggas comprising monofluoromethane (CH₃F), trifluoromethane (CHF₃),tetrafluoromethane (CF₄), hexafluoroethane (C₂F₆), or nitrogentrifluorude (NF₃).

In any case, the opening 145 has substantially vertical sides, i.e., thesidewall of the mold layer 140 that defines the sides of the opening 145is substantially perpendicular to the top surface of the substrate 100,because the mold layer 140 is not formed of an oxide.

Referring to FIG. 4, a barrier layer is formed (not shown) on thesubstrate 100 to cover the top surfaces of the plug 120 and theinsulating interlayer 110 exposed by the opening 145 and the sides ofthe opening 145. Then the barrier layer is anisotropically etched toform a barrier layer pattern 160 on the sides of the opening 145.

The barrier layer may be formed of at least one material selected fromthe group consisting of silicon oxide, titanium oxide, aluminum oxide,tantalum oxide, silicon nitride, silicon oxynitride, siliconcarbonitride, germanium oxide, germanium nitride, germanium oxynitrideand germanium carbonitride. In this embodiment, the barrier layerpattern 150 is formed to a thickness of several angstroms or tens ofangstroms. To these ends, the barrier layer may be formed by a CVDprocess, an ALD process, a molecular beam epitaxy (MBE) process, or thelike

Referring to FIG. 5, a lower electrode 160 is formed on in the opening145, i.e., over the exposed top surfaces of the plug 120 and theinsulating interlayer 110 and a sidewall of the barrier layer pattern150. Accordingly, the lower electrode is cup-shaped or cylindrical. Thelower electrode 160 may be formed of a metal or a metal nitride on thesubstrate 100. For example, a lower electrode layer may be formed oftitanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), tungsten(W), copper (Cu), titanium nitride, tantalum nitride, or tungstennitride on the substrate. The lower electrode layer may be a conformallayer formed on the substrate 100 so as to not only cover the barrierlayer pattern 160, etc, but so as to cover the upper surface of the moldlayer 140, as well.

Additionally, a sacrificial layer pattern 165 may then be formed to fillthe remaining portion of the opening 145. In particular, the sacrificiallayer pattern 165 may be formed of an oxide. Even more specifically, theoxide may be propylene oxide (PDX), phenyltriethoxysilane (PTEOS),boro-phosphoro silicate glass (BPSG), or phosphor silicate glass (PSG),for instance. Furthermore, the oxide as a sacrificial layer may beformed to such a thickness as to fill the remaining portion of theopening 145 and cover the lower electrode layer on the mold layer 140.

Then a chemical mechanical polishing (CMP) process and/or an etch-backprocess may be performed to remove upper portions of the lower electrodelayer and the sacrificial layer until a top surface of the mold layer140 is exposed.

Alternatively, the lower electrode 160 is formed to fill the opening 145(i.e., the sacrificial layer pattern 165 is not formed). In this case,the lower electrode 160 has the form of a pillar.

Referring to FIG. 6, the mold layer 140, the sacrificial layer pattern165 and the barrier layer pattern 150 are removed. In this process, theetch stop layer 130 may be removed together with the mold layer 140, thesacrificial layer pattern 165 and the barrier layer pattern 150. Forexample, the mold layer 140, the sacrificial layer pattern 165 and thebarrier layer pattern 150 are removed by a wet etching process.

Referring to FIG. 7, a dielectric layer 170 is formed on the insulatinginterlayer 110 to cover the lower electrode 160, and an upper electrode180 is formed on the dielectric layer 170.

The dielectric layer 170 may be formed of silicon oxide, silicon nitrideor a metal oxide having a high dielectric constant. Examples of themetal oxide that may be used include tantalum oxide, hafnium oxide,aluminum oxide, and zirconium oxide. These materials may be used aloneor in combination. Furthermore, the dielectric layer 170 may be formedby a CVD process, a PVD process, an ALD process, or the like.

The upper electrode 180 may also be formed by a CVD process, a PVDprocess, an ALD process, or the like. Furthermore, the upper electrode180 may be a blanket layer, like that shown in FIG. 7, or a relativelythin conformal layer having a uniform thickness.

In the above-described embodiment of a method of forming a capacitor inaccordance with the inventive concept, the lower electrode 160 is formedon a barrier layer pattern so that the mold layer 140 and the lowerelectrode 160 do not contact each other. As a result, a metal silicidelayer is not formed. Accordingly, the dielectric layer 170 may have auniform thickness, unlike a dielectric layer formed on a metal silicidelayer. Hence, a capacitor formed according to any of the methodsdescribed above may have all of those desirable characteristics providedby a uniformly thick upper electrode. Additionally, the dielectric layer170 is readily formed because the opening 145 is not constricted by ametal silicide layer. Still further, the lower electrode 160 may have avertical sidewall even at a high aspect ratio because the opening 145,in which the lower electrode 160 is formed, is itself formed in a moldlayer that is not an oxide.

Another embodiment of a method of forming a capacitor in accordance withthe inventive concept will now be described with reference to FIGS. 8 to13. The method is similar to that shown in and described with referenceto FIGS. 1 to 7 except for the forming of the barrier layer. Therefore,mainly only the differences between the embodiments will be described indetail hereinafter.

Referring to FIG. 8, an insulating interlayer 110 is formed on asubstrate 100, and a plug 120 is formed through the insulatinginterlayer 110. Then, an etch stop layer 130 and a mold layer 140 aresequentially formed on the insulating interlayer 110 and the plug 120.

Referring to FIG. 9, part of the mold layer 140 is removed to form anopening 145.

Referring to FIG. 10, the mold layer 140 having the opening 145therethrough is oxidized to form a barrier layer 152 on exposed surfacesof the mold layer 140 including a sidewall surface defining the sides ofthe opening 145. As a result, the barrier layer 152 is of silicon oxide.

The oxidation process may be a radical oxidation process, anozone-flushing process, a thermal oxidation process, or a dry oxidationprocess. For example, a radical oxidation process may be performed onthe mold layer 140 to form silicon oxide having a uniform thickness onthe sidewall and a top surface of the mold layer 140. Such a radicaloxidation process may be performed using a source gas including nitrogenor oxygen under a pressure of about 0.1 to about 1 torr. In this way,the barrier layer 152 of silicon oxide may be formed to a thickness ofseveral angstroms or tens of angstroms, for example.

Referring to FIG. 11, the portion of the etch stop layer 130 exposed bythe opening 145 is then removed to expose a top surface of the plug 120.In this case, i.e., in the case of removing the exposed portion of theetch stop layer 130 after the oxidation process, an oxidation layer isnot formed on the plug 120.

In addition, the portion of the barrier layer 152 formed on the topsurface of the mold layer 140 may be removed by an etching process. Inthis case, a barrier layer remaining on the sides of the opening 145 asa barrier layer pattern (not illustrated).

Referring to FIG. 12, a lower electrode 160 is then formed on the bottomof the opening 145 and sidewall of the barrier layer 152, and asacrificial layer pattern 165 may be formed on the lower electrode 160to fill what remains of the opening 145 (or the lower electrode 160 maybe formed to fill the opening 145 completely).

Referring to FIG. 13, the mold layer 140, the sacrificial layer pattern165 and the barrier layer 152 are removed. Then a dielectric layer 170and an upper electrode 180 are sequentially formed on the insulatinginterlayer 110 to cover the lower electrode 160.

Another embodiment of a method of forming a capacitor in accordance withthe inventive concept will be described with reference to FIGS. 14 to19. This embodiment is also similar to that shown in and described withreference to FIGS. 1 to 7 except for the forming of the barrier layer.Thus, mainly only the differences between these embodiments will bedescribed in detail hereinafter.

Referring to FIG. 14, an insulating interlayer 110 is formed on asubstrate 100, and a plug 120 is formed through the insulatinginterlayer 110. Then an etch stop layer 130 and a mold layer 140 aresequentially formed on the insulating interlayer 110 and the plug 120.

Referring to FIG. 15, part of the mold layer 140 is removed to form anopening 145.

Referring to FIG. 16, the mold layer 140 having the opening 145therethrough is then nitrided to form a barrier layer 154 on thesidewall of the mold layer 140 that defines the sides of the opening 145and the top surface of the mold layer 140. In this case, the barrierlayer 154 comprises silicon nitride.

The nitridation process may be a plasma nitridation process usingammonia (NH₃) or nitrogen (N₂) as source gas, or a thermal nitridationprocess. As an example, the mold layer 140 may be formed of polysiliconand subjected to a plasma nitridation process using ammonia as sourcegas to form a layer of silicon nitride having a uniform thickness on thesidewall and top surface of the mold layer 140. The source gas may beprovided under a pressure of about 0.1 to about 1 torr. The resultingbarrier layer 154 of silicon nitride may be formed to a thickness ofseveral angstroms or tens of angstroms in this process.

Referring to FIG. 17, the exposed portion of the etch stop layer 130 maythen be removed to expose the top surface of the plug 120. In this way,a nitride layer is not formed on the plug 120. Also, that portion of thebarrier layer 154 which extends along the top surface of the mold layer140 may be removed together with the exposed portion of the etch stoplayer 130. In this case, a barrier layer pattern 156 is formed on thesidewall of the opening 145.

Referring to FIG. 18, a lower electrode 160 is then formed in theopening 145. Furthermore, in the case in which the lower electrode 160is formed as a conformal layer of conductive material, a sacrificiallayer pattern 165 is formed on the lower electrode 160 to fill whatremains of the opening 145.

Referring to FIG. 19, the mold layer 140, the sacrificial layer pattern165 and the barrier layer pattern 156 are then removed. Again, withrespect to this part of the method, the etch stop layer 130 may beremoved together with the mold layer 140, the sacrificial layer pattern165 and the barrier layer pattern 156.

Next, a dielectric layer 170 and an upper electrode 180 are sequentiallyformed on the insulating interlayer 110 to cover the lower electrode160.

A method of manufacturing a semiconductor device in accordance with theinventive concept will now be described in detail with reference toFIGS. 20 to 24.

Referring to FIG. 20, an isolation layer 205 is formed at the upperportion of a substrate 200. In this example, the isolation layer 205 isformed by a shallow trench isolation (STI) process.

Next, a gate insulation layer, a gate electrode layer and a gate masklayer are sequentially formed on the substrate 200. The gate insulationlayer may be formed of silicon oxide or a metal oxide. The gateelectrode layer may be formed of metal or doped polysilicon. The gatemask layer may be formed of silicon nitride. In any case, the gateinsulation layer, the gate electrode layer and the gate mask layer arethen patterned by a photolithography process to form a plurality of gatestructures 210 each of which includes a gate insulation layer pattern212, a gate electrode 214 and a hard mask 216 sequentially stacked onthe substrate 200.

Impurities are then implanted into the substrate 200 using the gatestructures 210 as an ion-implantation mask to form first and secondimpurity regions 207 and 209 at upper portions of the substrate 200adjacent to the gate structures 210. The first and second impurityregions 207 and 209 serve as source/drain regions of the transistors.

Furthermore, spacers 218 of silicon nitride, for example, may be formedon sidewalls of gate structures 210.

Referring to FIG. 21, a first insulating interlayer 220 is then formedon the substrate 200 to cover the gate structures 210 and the spacers218. Part of the first insulating interlayer 220 is then removed to formfirst holes (not shown) exposing the impurity regions 207 and 209. Inthis example, the first holes are self-aligned with the impurity regions207 and 209 by the gate structures 210 and the spacers 218.

A first conductive layer is formed on the exposed impurity regions 207and 209 and the first insulating interlayer 220 to such a thickness asto fill the first holes. The first conductive layer may be formed ofmetal or doped polysilicon. The first conductive layer may then beplanarized, until a top surface of the first insulating interlayer 220is exposed, to form first and second plugs 227 and 229 electricallyconnected to the first and second impurity regions 207 and 209,respectively. In this example, the first plug 227 serves as a bit linecontact.

A second conductive layer (not shown) is formed on the first insulatinginterlayer 220 to contact the first plug 227. The second conductivelayer may be formed of metal or doped polysilicon. The second conductivelayer is then patterned to form a bit line (not shown). Next, a secondinsulating interlayer 230 is formed on the first insulating interlayer220 to cover the bit line. The second insulating interlayer 230 is thenetched to form a second hole (not shown) exposing the second plug 229. Athird conductive layer is then formed on the second plug 229 and thesecond insulating interlayer 230 to such a thickness as to fill thesecond hole. The third conductive layer may be formed of metal or dopedpolysilicon. Furthermore, the third conductive layer is planarized by aCMP process and/or an etch-back process, until a top surface of thesecond insulating interlayer 230 is exposed, to form a third plug 235filling the second hole. The second and third plugs 229 and 235collectively serve as a capacitor contact.

In another example of this embodiment, the second plug 229 is not formedin the first insulating interlayer 220. Rather, an opening is formedthrough the first and second insulating interlayers 220 and 230 toexpose the second impurity region 209, and the third plug 235 is formedin such an opening in contact with the second impurity region 209. Thatis, in this example, the plug 235 serves as a capacitor contact alone.

Referring to FIG. 22, an etch stop layer 240 and mold layers 250, 270and 290 are sequentially formed on the second insulating interlayer 230and the third plug 235. The mold layers 250, 270 and 290 may be formedof polysilicon or silicon doped with impurities. In the latter case, theimpurities may be carbon (C), boron (B), phosphorous (P), nitrogen (N),aluminum (Al), titanium (Ti), oxygen (O), or arsenic (As).

Furthermore, supporting layer patterns 260 and 280 also are formed onthe mold layers 250 and 270, respectively, so as to extend betweenadjacent ones of the mold layers 250, 270 and 290. More specifically, afirst supporting layer is formed on the first mold layer 250, and thefirst supporting layer is patterned to form the first supporting layerpattern 260. Likewise, a second supporting layer is formed on the secondmold layer 270, and the second supporting layer is patterned to form thesecond supporting layer pattern 280. The supporting layer patterns 260and 280 are formed of material having an etching selectivity withrespect to the mold layers 250, 270 and 290, e.g., silicon oxide,silicon nitride, or silicon oxynitride.

As will become clearer from the description below, the supporting layerpatterns 260 and 280 connect certain numbers of the capacitors toprevent the capacitors from leaning or collapsing once the mold layersare removed. In this example, three mold layers and consequently, twosupporting layer patterns are formed; however, the method is not solimited as the number of supporting layer patterns (and thus, moldlayers on which they are respectively formed) depends on the aspectratio of the capacitors to be formed.

Referring to FIG. 23, portions of each of the first to third mold layers250, 270 and 290, the first and second supporting layer patterns 260 and280 and the etch stop layer 240 are removed to form an opening (notillustrated) exposing a top surface of the third plug 235. Furthermore,a barrier layer is formed in the opening and in particular, along theexposed top surface of the third plug 235 and the sidewall that definesthe sides of the opening. The barrier layer is then anisotropicallyetched to form a barrier layer pattern 300 along the sides of theopening. In this respect, the barrier layer may be formed by any of theembodiments of FIGS. 1-19 described above. In addition, the supportinglayer patterns 260 and 280 are formed of material having an etchingselectivity with respect to the barrier layer.

For example, the barrier layer may be formed of silicon oxide, siliconnitride, aluminum oxide, tantalum oxide, etc. by a CVD process, an ALDprocess, or a molecular beam epitaxy (MBE) process.

Alternatively, the barrier layer may be formed of silicon oxide by anoxidation process, i.e., by oxidizing the mold layers 250, 270 and 290.Instead, the barrier layer may be formed of silicon nitride by nitridingthe mold layers 250, 270 and 290. In either of these cases, as has beendescribed above, the etch stop layer 240 is removed to expose the topsurface of the third plug 235 after the barrier layer is formed.Accordingly, the silicon oxide or silicon nitride is not formed on thethird plug 235.

Referring still to FIG. 23, a cup-shaped or cylindrical lower electrode310 is formed in the opening, i.e., on the exposed top surface of thethird plug 235 and the sidewall of the barrier layer pattern 300. Then,a sacrificial layer pattern 315 is formed to fill what remains of theopening.

More specifically, a lower electrode layer is formed conformally on thestructure comprising the third plug 235, the insulating interlayer 230,the mold layers 250, 270 and 290 and the supporting layer patterns 260and 280. A blanket sacrificial layer is then formed on the lowerelectrode layer to such a thickness as to fill the remaining portion ofthe opening. The lower electrode layer and the sacrificial layer arethen planarized by a chemical mechanical polishing (CMP) process and/oran etch-back process, until a top surface of the third mold layer 290 isexposed, to form the lower electrode 310 and the sacrificial layerpattern 315.

Alternatively, the lower electrode 310 may be formed to fill the openingcompletely. In this case, the lower electrode 310 has the form of apillar.

Referring to FIG. 24, the mold layers 250, 270 and 290, the sacrificiallayer pattern 315 and the barrier layer pattern 300 are removed. At thistime, the etch stop layer 240 may be removed together with the moldlayers 250, 270 and 290, the sacrificial layer pattern 315 and thebarrier layer pattern 300.

Next, a conformal dielectric layer 320 is formed on the secondinsulating interlayer 230 to cover the lower electrode 310, and ablanket upper electrode 330 is formed on the dielectric layer 320.Alternatively, a conformal upper electrode, i.e., a relatively thinupper electrode having a uniform thickness, is formed on the dielectriclayer 320.

Finally, embodiments of the inventive concept and examples thereof havebeen described above in detail. The inventive concept may, however, beembodied in many different forms and should not be construed as beinglimited to the embodiments described above. Rather, these embodimentswere described so that this disclosure is thorough and complete, andfully conveys the inventive concept to those skilled in the art. Thus,the true spirit and scope of the inventive concept is not limited by theembodiment and examples described above but by the following claims.

What is claimed is:
 1. A method of manufacturing a capacitor,comprising: forming a mold layer, comprising silicon but excludingoxides of silicon, on a substrate; forming an opening extending throughthe mold layer, wherein the opening has a bottom and sides; forming abarrier layer along the sides of the opening; forming a lower electrodein the opening including over the barrier layer, wherein the barrierlayer prevents a reaction from occurring between the lower electrode andthe mold layer; removing the mold layer and the barrier layer; andsequentially forming a dielectric layer and an upper electrode on thelower electrode.
 2. The method of claim 1, further comprising: formingan insulating interlayer on the substrate before the mold layer isformed; and forming a contact plug through the insulating interlayer,and wherein the forming of the opening through the mold layer comprisesforming the opening to expose a top surface of the contact plug.
 3. Themethod of claim 1, wherein the forming of the barrier layer comprises:forming barrier material along the bottom and sides of the opening andalong a top surface of the mold layer; and anisotropically etching thebarrier material to remove the barrier material from the bottom of theopening and the top surface of the mold layer.
 4. The method of claim 1,wherein the forming of the barrier layer comprises forming barriermaterial on the substrate by a chemical vapor deposition process, anatomic layer deposition process or a molecular beam epitaxy process. 5.The method of claim 4, wherein the barrier material is at least onematerial selected from the group consisting of silicon oxide, titaniumoxide, aluminum oxide, tantalum oxide, silicon nitride, siliconoxynitride, silicon carbonitride, germanium oxide, germanium nitride,germanium oxynitride and germanium carbonitride.
 6. The method of claim4, wherein the barrier layer is formed to a thickness of severalangstroms or tens of angstroms.
 7. The method of claim 1, wherein theforming the barrier layer comprises oxidizing a sidewall of the moldlayer exposed by the opening.
 8. The method of claim 7, wherein theoxidizing is executed by subjecting the mold layer to a radicaloxidation process, an ozone flushing process or a thermal oxidationprocess.
 9. The method of claim 1, wherein forming of the barrier layercomprises nitriding a sidewall of the mold layer exposed by the opening.10. The method of claim 9, wherein the nitriding comprises subjectingthe mold layer to an ammonia plasma nitridation process, a nitrogenplasma nitridation process or a thermal nitridation process.
 11. Themethod of claim 1, wherein the forming of the mold layer comprisesforming a layer selected from the group consisting of doped or undopedpolysilicon, on the substrate.
 12. A method of manufacturing asemiconductor device, comprising: forming a transistor at an upperportion of a substrate, the transistor having a gate structure and animpurity region; forming an insulating interlayer on the substrate andwhich covers the transistor; forming a contact plug extending throughthe insulating interlayer; forming at least one mold layer, comprisingsilicon but excluding oxides of silicon, on the insulating interlayerand the contact plug; forming an opening through the at least one moldlayer that exposes top surfaces of the contact plug and the insulatinginterlayer, wherein the opening has a bottom and sides; forming abarrier layer on the sides of the opening; forming a lower electrode inthe opening including over the exposed top surfaces of the contact plugand the insulating interlayer, and the barrier layer, wherein thebarrier layer prevents a reaction from occurring between the lowerelectrode and the mold layer; removing the mold layer and the barrierlayer; and sequentially forming a dielectric layer and an upperelectrode on the lower electrode.
 13. The method of claim 12, whereinthe forming of the barrier layer comprises: forming barrier materialalong the bottom and sides of the opening and a top surface of the moldlayer; and anisotropically etching the barrier material to remove thebarrier material from the bottom of the opening and the top surface ofthe mold layer.
 14. The method of claim 13, wherein the forming of thebarrier layer comprises forming barrier material on the substrate by achemical vapor deposition process, an atomic layer deposition process ora molecular beam epitaxy process.
 15. The method of claim 14, whereinthe barrier material is at least one material selected from the groupconsisting of silicon oxide, titanium oxide, aluminum oxide, tantalumoxide, silicon nitride, silicon oxynitride, silicon carbonitride,germanium oxide, germanium nitride, germanium oxynitride and germaniumcarbonitride.
 16. The method of claim 12, wherein the forming of themold layer comprises forming a layer selected from the group consistingof doped or undoped polysilicon, on the substrate.
 17. The method ofclaim 12, wherein the forming of at least one mold layer comprisesforming a plurality of mold layers, each comprising silicon butexcluding oxides of silicon, on the insulating interlayer and thecontact plug, and further comprising forming on each of at least one ofthe mold layers after it is formed a capacitor support having an etchselectivity with respect to the material of the mold layers, and whereinthe opening is formed through the support.
 18. A method of manufacturinga capacitor, comprising: forming a mold layer comprising doped orundoped polysilicon on an upper surface of a substrate; etching the moldlayer to form an opening, extending through the mold layer, and whichhas a bottom and sides that are substantially perpendicular to the uppersurface of the substrate; forming a barrier layer along the sides of theopening, wherein the barrier layer is of at least one material selectedfrom the group consisting of silicon oxide, titanium oxide, aluminumoxide, tantalum oxide, silicon nitride, silicon oxynitride, siliconcarbonitride, germanium oxide, germanium nitride, germanium oxynitrideand germanium carbonitride; forming a lower electrode of a metal ormetal nitride in the opening including over the barrier layer; removingthe mold layer and the barrier layer; and sequentially forming adielectric layer and an upper electrode on the lower electrode.
 19. Themethod of claim 18, wherein the etching is a dry etch in which the moldlayer is exposed to etching gas selected from the group consisting ofhydrogen fluoride (HF), hydrogen bromide (HBr), tetrafluoromethane(CF₄), hexafluoroethane (C₂F₆), trifluoromethane (CHF₃), difluoromethane(CH₂F₂), methyl bromide (CH₃Br), chlorotrifluoromethane (CClF₃),trifluorobromomethane (CBrF₃), carbon tetrachloride (CCl₄), sulfurhexafluorid (SF₆), chlorine (Cl₂), and nitrogen trifluorude (NF₃). 20.The method of claim 18, wherein the etching is a wet etch in which themold layer is wetted by a solution selected from the group consisting ofsolutions of hydrogen fluoride (HF), ammonium hydroxide (NH₄OH),potassium hydroxide (KOH), and sodium hydroxide (NaOH), and a bufferedoxide etch (BOE) solution.